Viettel IC Design Center (VIC) tuyển dụng kĩ sư điện tử viễn thông

Viettel IC Design Center (VIC) is looking for 10+ RTL engineers, 5+ Verification engineers, 5+ Backend Physical Design engineers, 2+ Algorithm engineers, 2+ Architect engineers. We welcome self-motivated and desired-to-learn fresh graduates, last-year students and, of course, experienced folks.

Students/engineers with hands-on projects/products directly relating to our requirements are preferred. Students/engineers graduated from honorable education programs (KSTN, KSCLC,..) are welcome. Being good at mathematics, analytical and critical thinking are plus. Master/doctoral degrees are advantages.

Please send your CVs in either English or Vietnamese (1 page preferred) to our email address: viettel.vic@gmail.com. (For convenience, we use gmail because our Viettel emails may filter out some non-working emails.)

Following are benefits, job descriptions, and requirements:

Benefits for all positions:

To be core parts of our projects to build the first world-class Chipset products of Vietnam.
Total gross compensation ranging from, but not limited to, $900 to $3000 per month.
Re-evaluate every 6 months/1 year based on work performance.
Performance-based scaling salary system in favor to qualified engineers.
Work in professional environments with licensed IC Design tools and cutting-edge design-assisting systems, which can’t be found elsewhere in Vietnam.
Opportunities to work with and to learn from top IC Design experts from all over the world.
Both fully-paid in-house and external training given by experienced engineers.
Opportunities to have abroad work-related travels.
Achievement rewards.
Holidays, day-offs, social insurance, maternity, ...

1. We want 10+ RTL Engineers

As a RTL engineer, you are in designing and integrating IPs for System-on-Chip solution using Digital IC design methodologies and design flows. You are also required to provide design documentation, description and information to other engineers and customers. verifications

Minimum Qualifications owning all aspects of assigned tasks ranging from RTL to

Degree (or transcript for last-year students) in electrical engineering (điện tử viễn thông) or computer engineering.
Knowledge of HDL and experience in RTL coding (VHDL/Verilog) for FPGA/ASIC.

Preferred qualifications but not limited to

Knowledge and experience of logic synthesis and timing analysis.
Experience in scripting languages such as Perl/Tcl/shell-scripting.
Knowledge and experience of ATPG.
Knowledge and experience of verification (SystemVerilog, UVM, OVM).
Knowledge and experience in SystemC/TLM.
Knowledge and experience of the MCU, MPU, DSP, bus, memory subsystem architecture and IO peripherals.
Experience with FPGA prototyping, IP integration, IC bring-up and test.
Knowledgeable in CMOS and FinFET technologies.
Master or PhD Degree in related fields.
Experience with Virtualizer, Architect Platform MCO, HAPS and Zebu.

2. We want 5+ backend Physical Design Engineer

As a Physical Design engineer you will be involved with all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.

Minimum Qualifications

Knowledge and experience in (Advanced) Digital Physical Implementation Flow (power aware design, floorplanning, low-power flow, libraries, IPs, Place&Route, Clock Tree Synthesis, Design for Test, IR-drop Analysis, Timing Analysis, Power Analysis, Sign-off).
Solid understanding of aspects of Physical construction, Integration and Physical Verification.
Experience in scripting languages such as Perl/Tcl/shell-scripting.

Preferred qualifications

Working knowledge of Basic SoC Architecture and HDL languages like VHDL/Verilog to be able with logic design team for timing fixes.
Power user of industry standard Physical Design & Synthesis tools.
Working knowledge of Extraction and STA methodology and tools.
Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.
Understanding CMOS technology nodes.

3. We want 5+ design Verification Engineers

As a Design Verification engineer, you will be responsible for verifying wireless digital baseband designs by developing test plans and verification environments and apply these to verify a broad spectrum of wireless designs. You will work closely with system and firmware engineers to formulate test cases and test vectors.

Minimum Qualifications

Verification test planning, testbench architect, assertions, problem solving and debug.
Experience with SystemVerilog using OVM or UVM.
Coverage driven verification (code/functional/assertion coverage).

Preferred qualifications

VHDL/Verilog, C/C++, Tcl/Perl/shell-scripting
Wireless or wireline modem communications or DSP background.
RTL design experience.
Experience with formal verification.
Experience with simulation acceleration tools.
General knowledge in design process, digital design, design (hw/sw) verification tools and techniques.

4. We want 2+ Digital Signal Processing Engineers

As a Digital Signal Processing engineer, you will involve in developing SoC solutions for wireless communication systems. You will work on system definition and design, performance analysis of digital baseband. You will work closely with the IC design teams and partners to create robust solutions meeting or exceeding the specifications. You must be a critical thinker, have strong self-direction, and be able to communicate clearly.

Typical job tasks include:

Develop/verify/validate algorithms, performance simulation for digital wireless communication systems.
Specifying signal processing logic for communication SOC.
Lab bring-up of reference boards, performance evaluation and system debugging.
Generate and own documentation detailing system and HW specifications and requirements.

Minimum Requirements:

Degree (or transcript for last-year students) in electrical engineering (điện tử viễn thông) with experience in wireless communications.
Good Mathematical and Analytical Skills.
Basic knowledge in wireless communication system.
Experience in Matlab or SystemVue.

Preferred Requirements:

Exposure and working knowledge in Architecture of wireless communication systems.
Knowledge or experience in Designing, implementing and integrating Digital Communications and Signal Processing Blocks.
Experience with massive MIMO, Channel Coding, channel estimation, FFT/DFT, equalizers,...
Experience in C/C++ Embedded Programming.

5. We want 2+ Architect Engineers

As an Architect engineer, the candidate will define system architecture for embedded chipsets architect for wireless communication system. The candidate will translate top-level chipset specifications into sub-block specifications. The candidate will work closely with internal cross-functional teams including algorithm engineers, hardware and software design engineers, and test engineers.