Công ty Faraday Technology (Đài Loan) tuyển dụng

Faraday believes people are the greatest asset and key success factor in a company. We create an inspiring workplace where each employee can contribute his/her expertise positively.

It's an important mission – delegating the right people in the right position and taking good care of them. Join us today for a rewarding and an exciting career future.

Human Resource Department

E-mail: globalhr@faraday-tech.com

 

Latest Opportunities

Job Positions Descriptions Location
SOC Physical Design Engineer Responsibilities
  • Responsible for ASIC physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations.
  • Responsible for physical verification including DRC, LVS and ESD checking.
Requirements
  • BS or MS degree in EE or CS related
  • Experience in Cadence Innovus flow or Synopsys ICC2 flow
  • Experience in hierarchical implementation, timing closure, IR drop analysis, crosstalk analysis is a plus
  • Experience in physical verification and layout editing is a plus
  • Experience in FinFet process node is a plus 
Ho Chi Minh, Vietnam
ASIC Consultant Engineer Responsibilities
  • Responsible for the main technical contact window and consultant of chip implementation from RTL-in/netlist-in to tape out for ASIC customers
  • Responsible for ASIC project management and coordination among internal supporting groups 
  • Responsible for DFT implementation, including MBIST, Scan insertion, IO level testing, JTAG and ATPG generation 
  • Responsible for ASIC constraint validation, including floorplan, timing, clock, package, power, and so on.
Requirements
  • Experienced in chip design flow and chip implementation flow
  • Familiar with EDA tools including PrimeTime, Debussy, Verilog-XL, Design Compiler, and formal verification tools 3. Interested in communicating with people
  • Familiar with DFT related flow and utilities is a plus
  • Experience in FinFet process node is a plus
Ho Chi Minh, Vietnam
Memory CAD Engineer Responsibilities
  • Responsible for running memory compiler to generate memory instance, including netlist and layout.
  • Responsible for memory characterization by using automatic characterization tools. The characterization flow including instance characterization and liberty generation.
  • Responsible for co-working with designers to verify characterization results and problem shooting.
  • Responsible for memory compiler enhancement to support new tech node.
Requirements
  • BS or MS degree in EE or CS related
  • Experience in library or memory characterization is a plus
  • Experience in running simulation and LPE tools is a plus
  • Understanding Synopsys liberty format is a plus
  • Familiar with script language such as c-shell and TCL is a plus
  • Experience in using layout editor or layout viewer is a plus
  • Experience in FinFet process node is a plus
Ho Chi Minh, Vietnam
Memory Design Engineer Responsibilities
  • Responsible for memory compiler (or instance) development including: create schematic, simulate, verify and analyze memory functionality, performance and statistical margin.
  • Responsible for ASIC project support: memory customization for PPA optimization including: communicate with internal or external customers to evaluate and optimize memory architecture to provide best memory solution.
  • Coordinate and participate in design related activities across multiple time zones
Requirements
  • BS or MS degree in EE related with 3+ years related memory design
  • Solid understanding of device physics, process and SRAM bit cell behavior
  • Experience in SPRAM, DPSRAM and 2PRF circuit design
  • Experience with embedded memory development in FinFET process nodes
  • Experience in FCI, TCAM, P2P and PDP is a plus
  • Ability to work with tight schedule and to conduct design experiments utilizing test chip vehicles.
  • Fluent with SKILL, Perl, Tcl, Python
Ho Chi Minh, Vietnam
Standard Cell Library Design Engineer Responsibilities
  • Responsible for standard cell library development and PPA optimization, including architectures, circuits, and design methodology
  • Support ASIC project customized standard cell for PPA optimization
  • Collaboration with foundries and peers of design methodology/flow team
Requirements
  • 5+ years of experience in standard cell library design
  • Solid understanding of device scaling challenges and circuit-process technology interactions applicable for advanced FinFET nodes
  • Familiar with standard cell layout
  • Knowledge of device characteristics and layout dependent effect
  • Experience in scripting, Perl or Tcl
  • Fluent English or Chinese Mandarin is a plus
Ho Chi Minh, Vietnam
Memory Layout Engineer Responsibilities
  • Responsible for memory compiler (or instance) layout
Requirements
  • BS or MS degree in EE related
  • Experience in SRAM memory instance and leaf cell layout
  • Experience in FinFet process node is a plus 
Ho Chi Minh, Vietnam