M.Eng. Brindha Devi. K.

Lecturer - Researcher of Department of Electronics & Telecommunications Engineering
Email: kathirvelbrindhadevi@tdtu.edu.vn
Office: C118

ACADEMIC/PROFESSIONAL BACKGROUND

Assistant Professor (15.07.2013 - Till Date) at Vivekanandha College of Engineering for Women, Tiruchengode, India Vivekanandha College of Technology for Women, Tiruchengode, India

Assistant Professor (26.06.2012 - 14.07.2013) at Vivekanandha College of Engineering for Women, Tiruchengode, India.
Paavai Engineering College, Tamil Nadu, India.

EDUCATIONAL BACKGROUND

M.E. Jan 2010 – Nov 2012 (Applied Electronics)

B.E. June 2006 – June 2009 (Electronics and communication)

AWARDS AND FELLOWSHIPS

  • University First Rank Holder (Gold Medalist) in 2012. 

Areas of Interest

  • Analog Communication Systems
  • Electron devices
  • VLSI
  • Optical Communication
  • Digital Communication
  • Satellite Communication
  • Electronic Circuits

LIST OF PUBLICATIONS

  1. K. Brindha Devi, D. Tamilselvi, K. Selvapriya, S. Kiruthiga “Analysis and Design of High Performance Low Power 8*8 Vedic Multiplier” in Int. J. Adv. Res. Innov. Edu. (IJRIIE), Volume 03, Issue 01, 2017 e-ISSN: 2395-4396.
  2. K. Brindha Devi, C. Aruna, D. Ilamathi, R. Divya Priya “Automatic Electronic toll e- ticketing system for transportation by using RFID and GSM technology “in Asian J. Appl. Sci Technol. (AJAST), Volume 01, Issue 01, Feb 2017.
  3. K. Praveen, C. Arul Kumar, K. Brindha Devi “Enhancement of voltage stability in transmission line using UPFC and IPFC” in Int. J. Mod. Trends Eng. Res (IJMTER) Volume 02, Issue 02, Feb 2015 e-ISSN :2349-9745.
  4. S. Dinesh, S. Ramachandran, K. Brindha Devi “Dynamic performance of DFIG under unbalanced condition using PID” in Int. J. Mod. Trends Eng. Res (IJMTER) Volume 02, Issue 02, Feb 2015 e-ISSN :2349-9745.
  5. G. Gowri Lakshmi, V. Abila, K. Brindha Devi “Implementation on STM-16 frame termination VLSI with High-Speed and Low Power GDI Techniques” in Int. J. Adv. Res in ELECTRICAL, Electronics and instrumentation Engineering (IJAREEIE) Volume 04, Issue 11, Nov 2015 e-ISSN: 2320-3765.
  6. G. Gowri Lakshmi, K. Brindha Devi “Design of STM-16 frame termination VLSI with GDI Techniques using SRAM” in Int. J. Scienti. Devt (IJSRD), Volume 04, Issue 03, May 2016 e-ISSN: 2321-0613.

WORKSHOPS AND CONFERENCES

  1. Participated in International Conference, SSM College of Engineering, Komarapalayam and presented a paper “Design and Analysis of Tree Multiplier Using Energy Efficient Adiabatic Logic”.
  2. Participated in International Conference, Teeja Shakthi Institute of Technology, Coimbatore and presented a paper “Design and Analysis of Finite Field Multiplier Using Reordered Normal Basis”.
  3. Participated in National Conference, KSR College of Technology, Tiruchengode and presented a paper “Low Power Analysis of Finite Field Multiplier by Means of Reordered Normal Basis”.
  4. Participated in National Conference, Saveetha Engineering College, Chennai and presented a paper “VLSI Implementation of Different Multipliers for Low Power”.
  5. Participated in International Conference, Vivekanandha College of Engineering for Women, Elayampalayam and presented a paper “Analysis and Design of High Performance Low Power 8*8 Vedic Multiplier”.
  6. Participated in International Conference, Vivekanandha College of Engineering for Women, Elayampalayam and presented a paper “Development of Automatic Toll E-Ticketing System For Transportation by Using RFID and GSM Technology”.
  7. Participated in International Conference, Al-Ameen Engineering College, Erode and presented a paper “Automatic Toll E-Ticketing System for Transportation by Using Rfid and Gsm Technology”.
  8. Attended workshop on “Lab View Based Signal Processing and Multisim Based Electronic Circuits and Simulation Applications” conducted by Vivekanandha College of Engineering for Women, Tiruchengode.

PROJECTS

Project: Design and Analysis of Finite Field Multiplier Using Reordered Normal Basis.

Description: An efficient VLSI analysis of finite field multiplier using reordered normal basis. The hardware architecture uses different building blocks such as TSPC domino logic building blocks and custom designed flip flops.

Project: System Architecture and Realization of MIMO Sphere Decoders on FPGA.

Description: There is a demand for faster wireless communications as this allow for new applications such as widespread wireless broadband internet access. Using multiple antennas at the transmitter and receiver to fulfill the demand for increased capacity.